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71M6545/71M6545H Data Sheet
IP1(SFR 0xB9) ( Table 34 ). If requests of the same priority level are received simultaneously, an internal
polling sequence as shown in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1 [x]
0
0
1
1
IP0 [x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table 34: I nterrupt Priority Registers ( IP0 and IP1 )
Register
IP0
IP1
Address
SFR 0xA9
SFR 0xB9
Bit 7
(MSB)
–
–
Bit 6
–
–
Bit 5
IP0[5]
IP1[5]
Bit 4
IP0[4]
IP1[4]
Bit 3
IP0[3]
IP1[3]
Bit 2
IP0[2]
IP1[2]
Bit 1
IP0[1]
IP1[1]
Bit 0
(LSB)
IP0[0]
IP1[0]
Table 35: Interrupt Polling Sequence
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Interrupt Sources and Vectors
Table 36 shows the interrupts with their associated flags and vector addresses.
Table 36: Interrupt Vectors
44
Interrupt Request Flag
IE0
TF0
IE1
TF1
RI0/TI0
RI1/TI1
IEX2
IEX3
IEX4
IEX5
IEX6
Description
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Serial channel 1 interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Interrupt Vector Address
0x0003
0x000B
0x0013
0x001B
0x0023
0x0083
0x004B
0x0053
0x005B
0x0063
0x006B
v2
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